1. Field of the Invention
This invention relates to a surface optical device apparatus which can be readily fabricated with good yield and is suitable for use in a structure constructed in a one- or two-dimensional array, its fabrication method, an optoelectronic device in which the surface optical device is integrated together with a Si integrated circuit (Si-IC), an optical wiring device using the surface optical device apparatus, an optical recording apparatus using the surface optical device apparatus, and related structures and devices.
2. Related Background Art
In recent years, the development of surface light emitting devices arranged in two-dimensional arrays has been desired. Among such devices, a vertical cavity surface emitting laser (VCSEL) is strongly expected since its threshold is low (approximately 1 mA), its power consumption is small, and it can be easily arrayed. Moreover, when a VCSEL is integrated with a Si-IC, the VCSEL can be speedily driven, and the device can be presented in a small package. Accordingly, such a structure can be advantageously applied to signal transmission between Si-IC's, to optical recording on a recording medium, and similar uses.
There are several methods of integrating an optical device and a Si-IC. In one method, an optical device is bonded to a Si substrate wherein Si-IC has been formed. In another method, a Si-IC and an optical device are integrated in a hybrid manner on a supporting substrate, such as a Si substrate, a printed circuit board (PCB), or a ceramic substrate.
As an example of the former method, there exists, as disclosed in Japanese Patent Application Laid-Open No. 9(1997)-223848, a method in which an epitaxial growth surface of a laser radiating layer is bonded to a Si-IC via a polyimide adhesive, and a GaAs growth substrate, on which the laser radiating layer had been grown, is removed by etching to obtain a surface emitting laser. FIG. 1 illustrates a cross section of this structure. An electrode of the surface emitting laser 100B fabricated by the above process is connected to an electrode 200A on the Si-IC substrate 200 via electrical wiring 400. Another electrode 100D is connected to a wiring pattern formed on the insulating layer 300 of polyimide. In such a structure, no alignment is needed between the optical device and the Si-IC. Further, additional processing, such as photolithography, can be conducted even after the integration, since only a functional layer of the optical device without its growth substrate is arranged on the Si and a step of the surface is hence small (about 5 μm). In FIG. 1, a light receiving device 100A, an electrode 100C of the device 100A and a layer 1000 of optical devices are illustrated as well.
As an example of the latter method, there exists, as disclosed in Japanese Patent Application Laid-Open No. 7(1995)-30209, a method in which a semiconductor substrate of an optical device is removed, the optical device in chip form is bonded to a film or the like, and the optical device is aligned with an electrode of an electronic circuit substrate and implemented in a flip-chip manner. FIGS. 2A to 2H illustrate the fabrication steps according to this method. After a functional layer 1106 is epitaxially grown on the semiconductor substrate 1101 as illustrated in FIG. 2A, an electrode 1109 for driving the optical device 1111 is formed as illustrated in FIG. 2B. The devices 1111 are then separated as illustrated in FIG. 2C, and the semiconductor substrate 1101 is removed by etching as illustrated in FIG. 2D. The devices 1111 are bonded to an extensible film 1114 as illustrated in FIG. 2E, and the film 1114 is extended to obtain chips of the optical device 1111 with only the functional layer 1106 as illustrated in FIG. 2F. The optical device 1111 is affixed at a desired area of an electronic circuit board 1117 with a pressing jig 1116. Thus, an optoelectronic multi-chip-module (MCM), in which the optical device 1111 is placed on the electronic circuit substrate 1117 in a hybrid integration manner, as illustrated in FIG. 2H, can be obtained. In FIGS. 2A to 2H, there are also illustrated a buffer layer 1102, a lower mirror 1103, an active layer 1104, an upper mirror 1105, an anode 1107, a cathode 1108, a mesa groove 1110, a separating groove 1112, a protective layer 1113, a spacing 1115, and an electrical wiring 1118.
There are significant problems with the structure disclosed in Japanese Patent Application Laid-Open No. 9(1997)-223848, however. Its thermal radiation characteristic is poor, and its luminary characteristics, such as light radiation efficiency and light output, are inferior to those of ordinary implementation structures, since the polyimide layer 300 is interposed between the optical devices 100A and 100B and the Si substrate 200. Further, since the fabrication process of the optical devices 100A and 100B is performed only after the functional layers of the optical devices are transferred to the Si substrate 200, limitations on the freedom of the process (i.e., on processing temperature, plasma processing, and the like) arise, due to concerns with preventing damage to the IC. Accordingly, the configurations of the optical devices 100A and 100B are also restricted.
Concerning the structure of Japanese Patent Application Laid-Open No. 7(1995)-30209, its mechanical strength is low due to a small thickness (ordinarily about 5 μm) of the functional layer 1106 without the substrate, though its thermal conductivity is good due to direct bonding between the electrodes. Accordingly, its handling is difficult, and its performance characteristics are likely to be decreased due to the introduction of crystallographic defects therein, and the like. Furthermore, two electrodes must be aligned for each device since the electric contact should be established on the side of the circuit board 1117 only. Therefore, high alignment precision is required, and costs increase accordingly.